发明名称 MOS MEMORY UNIT
摘要 PURPOSE:To reduce the power consumption of memory cell, by lowering the voltage fed to the memory cell, during the waiting operation of peripheral circuit. CONSTITUTION:When the peripheral circuit is waiting condition, the low level voltage is fed to the terminal 90, MOSFET 67 of the comparison circut 2000 is at interrupting condition, and the power line 80 of the memory cell 1000 is kept at high potential with the reduction of the channel resistance of MOSFET 50. When the peripheral circuit is in waiting operation, high level voltage is fed to the terminal 90, conducting FET 67 and making the comparison circuit 2000 into operating condition. The comparison circuit 2000 adopts the type of differential amplifier, which compares the voltage of the reference voltage generation circuit 3000 and that of the power supply line 80. The channel resistance of FET 50 is increased and the voltage of the power supply line 80 is taken equal as the reference voltage. During waiting condition, since the voltage fed to the memory cell is decreased, the power consumed in the memory cell can be reduced.
申请公布号 JPS54114929(A) 申请公布日期 1979.09.07
申请号 JP19780022666 申请日期 1978.02.27
申请人 NIPPON ELECTRIC CO 发明人 TAKAHASHI KAZUKIYO
分类号 G11C11/41;G11C11/417;G11C14/00 主分类号 G11C11/41
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