| 摘要 |
PURPOSE:To make a high-speed access possible in either of byte unit and word unit by connecting all bits of an address line except lower n-number bits to M-number memory parts commonly in case that a word length is expressed by M=2<n>-number bytes or characters. CONSTITUTION:When a word length is four bytes, main memory 2 has memory part 7 of M0 to M3 where data can be read and written in byte unit, and all bytes except lowest byte M0 are connected to selection circuit 5 commonly. First, in case of data write in byte unit, memory control circuit 3 issues a signal to instruct selection circuits 41 to 43 to select lowest byte WD0, and WD0 is written in memory part M1. That is, the processing is performed according to the state of lower two bits. In case of data write in word unit, memory control circuit 3 issures a signal to select bytes WD1 to WD3 corresponding to selection circuits 41 to 43, and data is written in memory parts M0 to M3 simultaneously by outputting a write signal to memory part 7. In this case, lower two bits are neglected. In data read, the processing is performed similarly to data write. |
