| 摘要 |
The invention relates to variable-threshold semiconductor memory elements, and to memory arrays of such elements. The elements 117 may be arranged in an array 115 of rows 118 and columns 119. Each element comprises source and drain electrodes 130, fixed threshold access gate regions 38 and 39 respectively connected to row conductor 124 and column conductors 122 and a variable-threshold memory gate 31 connected to a row conductor 44. The conductors 122 and 124 permit adjoining elements to be written at different times, so that adjacent columns 119 need not be isolated from each other, and a common source-drain line 130 can serve as the drain electrode of one element and the source electrode of the next. |
