| 摘要 |
<p>PURPOSE:To make it possible to reduce the power consumption of a CMOS logic circuit, by reducing the power at the stand-by time while no logical operation is done, by making the CMOS logic circuit operate intermittently. CONSTITUTION:During logical operation, clock pulse (a) is supplied from input terminal 4 to terminal 6 via AND gate 2. When there is the latency time of logic circuit 1 from prescribed logic operation until the start of the next operation, clock forbidden signal (b) is generated from output terminal 7 to hold output O of flip- flop circuit 3 at level ''0'' and to inhibit a clock signal from passing through AND gate 2, thereby preventing the transmission of signals to terminal 7. The CMOS logic circuit therefore stops operating as shown by (e) until a reset signal is inputted to flip-flop circuit 3 and, in consequence, average power consumption at the stand- by time can almost be ignored, so that the reduction of power consumption can be realized.</p> |
