| 摘要 |
PURPOSE:To reduce write time by changing one or both of the width and concentration of the base region of a transistor which becomes the passage gate of information current and a memory transistor thereby changing common emitter current amplification factor at the time of constituting a memory cell by the use of two I<2>L gate circuits. CONSTITUTION:An N type layer 2 is epitaxially grown on an N<+> type substrate 1 and three P type regions 3 thru 5 are diffusion-formed there. At this time, part of regions 4 and 5 are so formed that the layer 2 remains right under the portions corresponding to the regions 6 and 7 out of the N<+> type regions 6 thru 9 provided later in these regions. Next, A P type region 10 encircled by the region 4 so as to be tangent to the layer 2 at the circumferential edge and a P type region 11 encircled by the region 5 so as to be tangent to the layer 2 at the circumferential edge are diffusion-formed. Thereafter, N<2> type regions 6 and 8 are provided in the region 4 and N<+> type regions 7 and 9 in the region 5. Here, the bottom faces of the regions 6 and 7 are made shallower than those of the regions 10 and 11. Thereafter word line pairs W and bit lines B0, B1 are respectively mounted. |
