| 摘要 |
PURPOSE:To read the memory block in parallel by only one reading pulse by dividing the memory unit constituting time switch into a plural number of blocks and allowing these blocks to have an access in parallel on the sequential side. CONSTITUTION:Information of input highway HWLI is fed into each memory unit by writing pulse Wp at writing timing W. When reading, R/W signal becomes ''0'', BS of each memory device block becomes ''1'' regardless of the output of decoder DEC, the output of entire memory is made effective, this memory output is inputted into latch circuit L1-Ln and held by reading pulse Rp. Since the reading address in not a low level bit corresponding to n in counter CTR output, the same address is designated n times and it is acceptable if the read out pulse Rp is generated once in any given position in n cycle and the acceptable cycle is 1/n of writing pulse WEp. |
