发明名称 DIGITAL COUNTER
摘要 PURPOSE:To decrease greatly the number of the component element of each stage as well as to reduce the signal transmission delay of each stage by constituting the unit stage of the counter with the steering-gate circuit and the bistable circuit. CONSTITUTION:Stage 9 consists of bistable circuit 25 comprising NOR gate 7 and 8 which are cross-coupled each other and steering-gate circuit 26 comprising AND gate 5 and 6 one input terminal of which is connected in common and the other input terminal is connected to one input terminal of NOR gate 7 and 8. The output of circuit 26 is supplied to the input terminal of next stage 14. In such constitution, the trigger pulse row is applied to input terminal A, and thus the signal obtained by dividing the trigger pulse into two emerges at the output side of circuit 26 to be then supplied to next stage 14. And the signals obtained by dividing the input into two are delivered in sequence from each of the subsequent stages. In this way, the counter is constituted with just the gate of four units of the stage, so the signal transmission delay is reduced greatly to be used up to a high frequency.
申请公布号 JPS54103664(A) 申请公布日期 1979.08.15
申请号 JP19780010962 申请日期 1978.02.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIZUGUCHI HIROSHI
分类号 H03K23/58;H03K23/00 主分类号 H03K23/58
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