发明名称 Programmed digital computer system - has three data buses each comprising several data memory circuits, one for each digit in computer
摘要 <p>The buses(3, 6, 7) transfer operands, instructions, intermediate and final results between respective inputs and outputs of a data memory(9) for storing data for the period of executing one instruction. It also has a program memory(1), a control unit(8), a control register unit(10), a computing unit(11), a data shifter(12), a masking unit(13) a data address unit(14), a data receive and transfer unit(15) and a instruction address unit(16) which generates the address of the next micro instruction. A control data memory(18) is connected to the other units and a data analysis bus(30). Pref. this increases the operation speed of the system and reduces the amount of hardware.</p>
申请公布号 FR2414754(A1) 申请公布日期 1979.08.10
申请号 FR19780000647 申请日期 1978.01.11
申请人 GUSEV VALERY 发明人
分类号 G06F5/01;G06F11/267;G06F15/78;(IPC1-7):06F13/00;06F3/04 主分类号 G06F5/01
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