发明名称 PARITY CIRCUIT
摘要 PURPOSE:To realize the parity circuit less in element number and short in propagation delay time. CONSTITUTION:P channel MOST and N channel MOST are switches operating oppositely each other to signal. For example, P channel MOST is conductive with the input signal 0 and N channel MOST is conductive with the input signal 1. As a result, the inverter circuit converting 0 of input signal into 1 is not required to be used. Also, it is not required to add the non-inversion signal and the inverting signal of one input signal to the parity circuit, and the number of input lines can be reduced.
申请公布号 JPS54101238(A) 申请公布日期 1979.08.09
申请号 JP19780007264 申请日期 1978.01.27
申请人 HITACHI LTD 发明人 YOSHIMOTO HIROYUKI
分类号 G06F11/10 主分类号 G06F11/10
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