发明名称 Input-output control circuit for FIFO memory
摘要 In transmitting data between a plurality of sequentially connected FIFO type memory elements by controlling a binary coded signal a circuit element is provided in a manner to correspond to each memory element, so as to indicate a data storage state. A circuit element comprises flip-flop constructed of two NOR circuits, the input of each NOR circuit being connected to an input control line or an output control line, and inverters each of which is connected to the output of the NOR circuit. The provision of such circuit element permits an automatic data transmission control according to a data storage state in a specified memory element and a data storage state in the next stage memory element.
申请公布号 US4163291(A) 申请公布日期 1979.07.31
申请号 US19760732965 申请日期 1976.10.15
申请人 TOKYO SHIBAURA ELECTRIC CO LTD 发明人 MORIYA, YOSHIAKI;SUZUKI, SEIGO
分类号 G06F5/08;G11C19/28;(IPC1-7):G11C7/00;G11C19/00 主分类号 G06F5/08
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