| 摘要 |
A clocked memory comprising a memory matrix having a plurality of memory cells arranged in rows and columns on a semiconductor substrate; a plurality of word select lines in said memory matrix, a plurality of bit lines crossing said select lines and connecting to said memory cells in each column; a drive circuit for driving said word select lines; a plurality of presence amplifiers connected to said bit lines; and a sense clock line parallel to said word select lines and connected to a gate of a transistor in said presence amplifier; and a presense drive circuit connected to said sense clock line and operated by a clock signal, said presense drive circuit having a transistor with controlled charging capability so as to conduct said transistor responsive to the charge of the memory cell in said each column.
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