发明名称 AD CONVERTER WITH HYSTERESIS CHARACTERISTICS
摘要 A summation unit (30) is connected between an analogue selection circuit (10) and the A/D converter (36) and also receives input from a D/A converter (52). The output from the A/D converter (36) is in binary form and is transferred to a memory unit (39) and thereafter to a multiplexer (50). The circuit has the property of incorporating a hysteresis effect in a feedback loop and thereby enabling some control to be exercised over the analogue signal. The first group of analogue signals enters through four terminals (2, 4, 6, 8) on the input side of the selector, and the second group from the D/A converter to produce the third group from the summator. Digital control signals enter via four input lines (20-26) and are supplied to the selector (10), memory (39) and multiplexer (50) as well as a digital display (64).
申请公布号 JPS5492047(A) 申请公布日期 1979.07.20
申请号 JP19780156775 申请日期 1978.12.15
申请人 MOTOROLA INC 发明人 RUUBEN UETSUKUSURAA
分类号 H03M1/08;H03M1/00 主分类号 H03M1/08
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