| 摘要 |
The circuit for controlling the data according to the desired mode and character size comprises latches (BU1-2) latching the data provided from a character ROM, shift register (SFG1-2) shifting the outputs of (BU1-2), OR gates (OR2-9, OR10-17) summing up the outputs of (SFG1-2) and curser enable signals (CUE, CLE), latches (BU3-4) latching the MSB of the outputs of (OR2,OR10), multiplexers (MUx1-5) multiplexing the latched MSB and the outputs of (OR2-9, OR10-17), a latch (BU5) latching the multiplexed data, and AND gates (A2-9) providing the data scanning pulses to display them on the LCD.
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