| 摘要 |
PURPOSE:To output a multi-fequency signal input as a pulse train from a holding circuit by resetting automatically the holding circuit, which the multi-frequency signal input at every frequency, each time it operates. CONSTITUTION:A multi-frequency input signal is caused to pass through low-pass filters 21 to 26 from input end 1, and a pertinent frequency signal is detected by signal detector circuits 31 to 36 and is inputted to FF 51 to 56 to be operated. Then, the output is taken out from output ends 61 to 66; and simultaneously, after each output of six frequencies is delayed by a fixed time in timing circuit 12 through OR circuit 11, FF 51 to 56 are rset according to control signal 14 which gives an input signal gate in AND circuit 13. Logic of OR circuit 11 is not operated by resetting FF 51 to 56, and timing circuit 12 is reset to return FF 51 to 56 to an initial state. This operation is repeated to take out a pulse train from output ends 61 to 66. |
