| 摘要 |
PURPOSE:To simplify the circuit constitution, by providing the pulse insertion and delete circuit, delivering only the first higher clock pulse if the phase of the internal clock pulse advances than the external clock pulse, and delivering the second higher clock pulse after synthesizing it with the first clock pulse on the time axis, if the phase is lagged. CONSTITUTION:The delete pulse F in a given time width is generated in the timing of external clock pulse Z1, and the first higher clock pulse G1 in formed, in which one pulse is deleted in the time width of the deleted pulse F with this pulse and the higher clock pulses B3 and B4. Simultaneously, the second higher clock pulse G2 is formed, in which two pulses are present only in the time width of the delete pulse by means of the pulse B5 inverting the polarity of the higher clock pulse and the delete pulse inverting the polarity. If the phase of the internal clock pluse Z2 advances the external clock pulse Z1, only the first higher clock pulse G1 is delivered and if lags, the second higher clock pulse is delivered after being synthesized with the first pulse. The pulse insertion and delete circuit plays a role of this operation. |
