发明名称 Thin-film electrical components
摘要 1,130,341. Printed circuits. WESTERN ELECTRIC CO. Inc. 5 Nov., 1965 [9 Nov., 1964], No. 46968/65. Addition to 1,125,394. Heading H1R. A thin film circuit is made by the selective sequential etching of a laminate, Fig. 1B, comprising a substrate 11 of glass or ceramic, a resistive layer 12 of tantalum nitride, a conductive anodizable layer 13 of metal, e.g. aluminium (or niobium), a layer 14 of tantalum, and a top layer 15 of highly conductive metal such as copper plates with palladium, or gold. Layers 12-15 are preferably deposited on substrate 11, as by sputtering or evaporation, in a continuous vacuum process. A first resist is applied to areas of layer 15 required to form terminals, and the layer is treated with a first etchant, e.g. ferric chloride or aqua regia (Figs. 2A, 2B, not shown). The first resist is removed, and a second resist is applied to the terminals and to the tantalum layer 14 where the latter is required for capacitor formation, and where the underlying aluminium is required for interconnections; parts of layers 13, 14 unprotected by the second resist are then removed, using hydrochloric acid or sodium hydroxide (Figs. 3A, 3B, not shown). The second resist is removed, and a third resist applied in its place, and also to the areas of resistive layer 12 to be retained. Unwanted areas of layer 12 are removed, using hot concentrated sodium hydroxide (Figs. 4A, 4B, not shown); an aqueous solution of hydrofluoric and nitric acids may alternatively be used, in which case the formation of an oxide layer between substrate 11 and layer 12 is desirable to prevent undercutting, as disclosed in Specification 962,015. After removal of the third resist, the exposed area of layer 14 is anodized at 32, Fig. 7B, to provide a capacitor dielectric layer; alternatively, a dielectric layer may be deposited. An upper capacitor electrode and lead layer 40, e.g. of gold, is applied, and the values of resistors are trimmed by anodization, as at 31a. If inductors are required, they may be formed by etching from layers 13 or 15; interconnections may alternatively be formed from layer 15; and in some cases layer 15 may be omitted altogether.
申请公布号 GB1130341(A) 申请公布日期 1968.10.16
申请号 GB19650046968 申请日期 1965.11.05
申请人 WESTERN ELECTRIC COMPANY, INCORPORATED 发明人 CHAPELLE EDWARD ALBERT LA
分类号 C23F1/02;H01B1/00;H01C7/00;H01C17/06;H01G4/40;H01L49/02 主分类号 C23F1/02
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