| 摘要 |
PURPOSE:To detect intermittent error of operation circuit with a set of operation circuit, by performing the same operation in a plurality number in the operation circuit, setting the result of operation to a plurality of registers, and performing subtraction among registers. CONSTITUTION:The stage forming circuit 23 continuously produces the instruction readout signal IF24, first and second signals 25 and 26 representing the operand readout stage, and operation stage signal 27, and also develops the stage signals 32 to 34 based on the basic clock signal 28. Further, based on the signals 32 to 34, the operation circuit 17 performs the same operation in a plural number of times, the result of operation is set to a plurality of operation registers 14 and 15, the subtraction between the registers 14 and 15 is made with the operation circuit 17, the result is detected with the zero detection circuit 37, and intermittent error caused by the operation circuit is detected. |
