发明名称 EXCLUSIVE LOGICAL SUM CIRCUIT
摘要 PURPOSE:To constitute the exclusive logical sum circuit with a few elements and to make easy multi-input, by locating C-MOSFET symmetrically. CONSTITUTION:PMOSP1 to P3 and NMOSN1 to N3, PMOSP4 to P6 and NMOSN4 to N6 are symmetrically arranged between the high potential VH and branch A and between the branch A and the low potential VL. When all the inputs are logically 0, no path is made between the branch A and the potential VL, FETP1, P2,P3 are conductive, and if they are logically 1, FETN1, N2, N3 are conductive, and in any case, ligical 1 is caused to the branch A and the output OUT has the logical 0. Further, if the inputs have one different ligical value at least, no path is present between the potential VH and the branch A. One of FETP4,P5,P6 and one of FETN4,N5,N6 are conductive, and the branch A is at logical 0 and the logical 1 is outputted. Thus, desired object can be achieved. Further, by adding FETP8, the operation speed at DC level can be inproved.
申请公布号 JPS5487159(A) 申请公布日期 1979.07.11
申请号 JP19770154337 申请日期 1977.12.23
申请人 FUJITSU LTD 发明人 MICHIGUCHI YOSHIAKI
分类号 H03K19/0948;H03K19/21 主分类号 H03K19/0948
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