| 摘要 |
<p>PURPOSE:To realize the clear operation surely without increasing the time constant, by taking the set input from the output of the time constant circuit for the latch circuit and reset input from the output of demultiplication circuit, and by forming the clear signal based on the output of the latch circuit. CONSTITUTION:The time constant circuit R1, C takes the power supply voltages VDD + and VSS - as input, and the signal urilizing the time difference between the leading of the power supply voltage and that of the output of the time constant circuit R1, C is used as the reset signal for FFF15 and F16 requiring time. Further, the latch circuits G2 and G3 take the output of the time constant circuit as set input and the output of frequency demiltiplication circuit as reset input, forming the clear signal based on the output of the latch circuits G2 and G3. Thus, sure clear operation can be realized without increasing the time constant CR.</p> |
