| 摘要 |
PURPOSE:To reduce the capacity of the clock oscillator circuit down to half as well as to sumplify the circuit constitution by changing the output of the clock oscillator circuit into the clock signals of different phases via the gate circuit. CONSTITUTION:Output signal CS of clock oscillator circuit 17 is delivered after conversion to clock signal CSb featuring the 180 deg. phase difference from clock signal CSa. And signal CSa is supplied to input terminal CK of FF11, 13 and 15 each, and signal CSb is supplied to terminal CK of FF12, 14 and 16 respectively. Thus, each clock signal makes FF11-16 function as the ring counter. |
