发明名称 |
Error test circuit for binary data - uses rectifier stage to produce nRZ signal passed through two threshold test levels and output logic circuit giving error free signal |
摘要 |
<p>The error test circuit for binary data accepts a read signal (RO) which may include an interference signal (SI). The signal read in is transferred to an NRZ-type read circuit which produces a rectified output submitted to a selection circuit with an upper (URO) and a lower (URU) threshold value level. The selection circuit consists of two threshold value stages with outputs each sent to one of two registers. The latter is connected to a multiplexer, the common output line from which continues through a parity check unit in parallel with a summation unit; The final stages include a comparator and a flip-flop. These stages produce an error free output.</p> |
申请公布号 |
DE2758390(A1) |
申请公布日期 |
1979.07.05 |
申请号 |
DE19772758390 |
申请日期 |
1977.12.28 |
申请人 |
SIEMENS AG |
发明人 |
SCHMIDT,HERBERT |
分类号 |
G06F11/10;G06F11/16;G11B20/18;(IPC1-7):11B5/09;06F11/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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