| 摘要 |
PURPOSE:To considerably reduce the number of wirings between superposed frequency divided signal generating part and the circuits making use of the outputs thereof by serially sending out plural stages of frequency divided signals corresponding to the scals frequencies of respective pitch names. CONSTITUTION:The frequency divided data forming part 40 of a superposed frequency divided signal generating part 18 subsequently series-shift the holding contents of FFs 1 thru 7 for delay during series addition operation and add the timing signals P from the transmission part 41 to the data of the lowest bits (bits of FF1). Controlling of whether this operation is performed or memory operation is performed is accomplished by the output of set-reset type FF57. When the output is ''1'', the signal of a shift line 58 becomes ''1'' and the holding data are shifted from the FF 7 to FF 1. Next, the data of the FF 1 are added to the signal P or the carrier signal from FF 54 for delaying in an adder 53 and then inputted to the FF7, the frequency dividing data Q1 thru Q7 whereby are then serially outputted via line 64, OR 65, AND 66. Thereby, the number of wirings between the associated circuits may be considerably reduced. |
