| 摘要 |
PURPOSE:To obtain a memory circuit which reduces the number of the input terminal and is also suited to the semiconductor integrated circuit device which can secure the high-speed performance, by providing the discriminating circuit which performs the quadruple identification of the input signal to select the address input signal. CONSTITUTION:Signal AO featuring the quadruple level is applied from the input terminal to 1st discriminator 4 featuring high potential threshold VRefa, 2nd discriminator 6 featuring low potential threshold VRefb and to 3rd discriminator 5 featuring middle potential threshold VRefo between discriminator 4 and 6 respectively. And the binary signal is delivered to the output of each of discriminators 4-6. The operation of discriminator 4 and 6 can be controlled complementarily by the output of discriminator 5, and the signal which discriminated the quadruple value of signal AO is delivered to the output of discriminator 4 and 6. Thus, the circuit is used as the input circuit which carries out the control for the memory circuit within the semiconductor integrated circuit device. |
