发明名称 SYNTHESIZER RECEIVER
摘要 PURPOSE:To increase the transient response and the frequency stability, by controlling VCO according to the output frequency of the frequency demultiplier and VCO of PLL. CONSTITUTION:The oscillation frequency of VCO 5 of the PLL frequency synthesizer 4 and the frequency corresponding to the frequency dividing ratio of the programmable frequency demultiplier 6 are compared with the circuit 21, and the positive or negative output pulse according to the magnitude of the both frequencies is superimposed on the DC control signal from LPF 9 and is fed to VCO 3, controlling the oscillation frequency. As a result, the time until the oscillation frequency is completely locked can be reduced.
申请公布号 JPS5481707(A) 申请公布日期 1979.06.29
申请号 JP19770149646 申请日期 1977.12.13
申请人 SONY CORP 发明人 SATOU TERUO
分类号 H03L7/113;H04B1/26 主分类号 H03L7/113
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