CLOCK SELECTING CIRCUIT

摘要

PURPOSE:To avoid data errors by frequency-dividing a free-running clock in a phase locked loop circuit when a clock sequence is switched, generating a frame clock, latching sequence selection order information, input clock interruption information and select information by means of the frame clock and generating select information. CONSTITUTION:When a clock sequence n1 comes to an interruption state, a PLO circuit 3 starts free running. The frequency divider 4 frequency-divides the free-running clock outputted from the PLO circuit 3 into the clock frequency 8KHz of a synchronous network, and gives it to FF5 as the frame clock. Consequently, select information given to a selector 2 from ROM11 through FF12 is synchronized with the free-running clock outputted from the PLO circuit 3. Thus, the PLO circuit 3 can absorb fluctuation even if the phase of a clock sequence n2 which the select information selects slightly fluctuates, and therefore the data errors are prevented from occurring.