| 摘要 |
Binary message signals arriving over a PCM link at a retransmitting station, with a predetermined average bit cadence subject to random variations, are cyclically written in an 8-stage buffer register under the control of an 8-pulse writing counter stepped by clock pulses extracted from the incoming bit stream. The contents of the buffer register are read out under the control of an 8-pulse reading counter stepped by a local pulse generator whose pulse rate substantially corresponds to the predetermined cadence. Any deviations of the actual bit rate from the predetermined cadence are detected in a phase comparator receiving mutually interleaved monitoring pulses, once per 8-bit cycle, from the two counters. The comparator comprises a flip-flop whose alternate setting and resetting by the two pulse trains produces a square wave of 50% duty ratio when the counters are in step; otherwise, the detected mean amplitude of the square wave adjusts the operating frequency of a quartz-controlled oscillator, forming part of the local pulse generator, to compensate for the deviation. |
