| 摘要 |
<p>PURPOSE:To enable to check the failure of the shift registers of the information transmission and reception section economically, by adding the shift registers mounted on two stages and two sets to the information transmission and reception section. CONSTITUTION:The parallel serial conversion shift register A in the information transmission section, delivery line L, and the serial parallel shift register B are provided, and the output of bf1, bf2, bb1 bb2 is fed to the check circuit CHK, including the information delivery shift registers a1 to an of n-stages, information reception shift registers of n-stages b1 to bn, two stages of shift registers af, af2, bf1, bf2 provided at the front edge of the shift registers for checking, two stages of checking shift registers ab1, ab2, bb1, bb2 provided at the front edge of shift registers. The information input to the shift register added to the shift register at the information transmission section is always taken as the logic level 0,1 or 1,0 and the inspection of the information output inputted to the shift registers added to the information reception section performs failure check of the shift registers in the information transmission and reception section.</p> |
