| 摘要 |
PURPOSE:To speed up a processing by using a three-stage latch type D type flip-flop instead of a two-stage latch type D type flip-flop in a master slave type. CONSTITUTION:The title multiplexer is provided with D type flip-flop DFFs 1 and 2, a selecting circuit SELECTOR 3 to selectively output data signals inputted to data signal input terminals D1 and D2 by the 'H' level or 'L' level of a selecting signal Se inputted to a selecting signal input terminal S, and a delaying circuit DELAY 4 for adjusting a timing. Instead of the conventional two-stage latch type DFF in the master slave type, the constitution is executed by using the three-stage latch type DFF. Consequently, the timing margin of the selecting signal is enlarged, and an output signal without a malfunction can be obtained from the selecting circuit 3. Thus, a high-speed operation can be realized. |
