FIFO look-ahead system

摘要

A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device. The input register to the predictor FIFO thereupon is emptied, and another data request may be made to main memory.