| 摘要 |
PURPOSE:To utilize the circuit for frequency-division multiplex communication, etc., by enabling it to operate with low power consumption and to attain rapid phase synchronization by controlling stable phase synchronization through phase comparison at a divided low frequency. CONSTITUTION:When reference signal (a) divided 1 is cut off, the update in memory 6 is stopped [The pulse width of phase difference signal (c) between signals (a) and (b) (outputs of phase comparator 2) is quantized and written in a stationary state] and the previous stage is memory-held. Then, voltage control crystal oscillator 4 free-scans until signal (a) arrives. When signal (a) is supplied again, the 2nd clock is regarded as its reference one to reset divider counter 7 by applying a reset pulse to it from reset pulse generator 5 and the contents of memory 6 are preset. As a result, comparator 2 is applied with the output signal of counter with a phase difference from the rise of the output signal of input divider 1 immediately before signal (a) is cut off, so that oscillator 4 will be applied with a control voltage equivalent to the phase difference right before signal (a) is cut off. |
