| 摘要 |
<p>PURPOSE:To obtain a circuit where a set range for delay time is wide and time change is easy, by inputting the data output of a fixed memory element as an address of the same fixed memory circuit and generating a delay time while updating successively the address according to constant clocks and making the address into a signal circulating state. CONSTITUTION:A delay circuit is constituted by ROM1 as a fixed memory circuit and latch resister 2 using a four-bit FF. in this constitution, data outputs D01 to D31 of ROM1 are connected to data inputs D02 to D32 of register 2, and Q0 of data outputs Q0 to Q3 of register 2 is connected to delay circuit output terminal 4, and Q1 to Q3 are connected to address inputs A0 to A3 of ROM1 respectively. Further, input terminal 3 of the circuit and clock terminal 5 are connected to chip enable input CE and clock input C of resister 2 respectively. When data of D01 written in ROM1 is changed, a delay time up to seven times as long as a clock signal can be generated.</p> |
