| 摘要 |
PURPOSE:To increase the information transfer speed between the memory unit and the requested unit, by splitting the memory unit of random access into a plurality of memory modules, and by providing the circuit group corresponding to each module and common sharing circuit group. CONSTITUTION:The request unit 1 continuously delivers two memory access requests and the simultaneous operation disignation signal on the signal line 53. Two memory access request signals, address information and memory information are delivered to the signal lines 30 to 32 in time-sharing manner, and are distributed to the circuit groups 12 to 17 corresponding to the memory element groups 2 and 4 via the distribution circuits 8 to 9. When the operation designation circuit 11 delivers the simultaneous operation signal, the memory element groups 2 and 3 simultaneously initiate the operation and two sequential operations are made with one execution operation. Thus, since a plurality of memory modules perform memory access simultaneously, the information transfer speed between the memory unit and the request unit can be increased. |
