发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To simplify the peripheral circuit of a memory by using a sequence control circuit, which varies the number of states in each cycle, to control the timing of the memory. CONSTITUTION:Memory 35 stores a program or data, and mode register 31 indicates the used mode of memory 35. Here, sequence control circuit 32 is provided which instructs the skip operation for each stage dependently upon contents set in register 31 and varies the stage in each cycle on a basis of this instruction, and further, address register 34 is provided which becomes available by the output of this circuit 32 and assignes the address of memory 35. Thus, circuit 32 which varies the number of states in each cycle is used to control the timing of memory 35, so that the peripheral circuit of memory 35 can be simplified.
申请公布号 JPS5475233(A) 申请公布日期 1979.06.15
申请号 JP19770142915 申请日期 1977.11.29
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TERAJIMA MITSUO
分类号 G06F12/06;G06F12/00;G11C8/18 主分类号 G06F12/06
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