| 摘要 |
PURPOSE:To prevent all the data bit of one set from being disapperated, belonging to the cycle with missing cycle of one regresh cycle, by constituting that the memory element of each bit has the order or refresh entirely different. CONSTITUTION:The refresh address medifying circuits 601 to 603 are located by one every memory element 412 group occupying the same bit location of each word and the address drivers 604 to 609 are located separately with the memory element group occupying the same bit location of each word. The circuits 601 to 603 invert some of the address signals SA7 to SA11 with a given law when the main memory control set refreshes the memory element, and the address signal values of MoA7 to 11, M1A7 to 11, M2A7 to 11 are all made different. Thus, the outputs BoA7...are all different to the same value of the refresh address counter 406 and each element group of DOUT is refreshed to the row number part not belonging to the same word. Thus, information missing is stopped to one bit and correction is immediately made. |
