发明名称 ARITHMETIC LOGIC OPERATION CIRCUIT
摘要 PURPOSE:To simultaneously process a plurality of data words and to speed up the processing, by performing parallel precessing operation through split of the arithmetic logic operation circuit, when a plurality of data words are stored logically in one word of the computer. CONSTITUTION:In the operation circuit having the arithmetic logic operation circuit ALU1 of lower 16-bit and ALU2 of upper 16-bit and providing the carry control circuit 3, ALU operation control circuit 4, data registers 5, 6 and output register 7, the function indicating two sets of ALU 1, 2 for split and consolidation is given to the control circuit 3. Further, in operating the data in 32-bit, the data from the bus 8 is allocated in the registers 5 and 6, the control signal D to the control circuit 3 is made in high level, the AND gate 9 provided with the control circuit 3 is opened, the carry signal CP from ALU 1 is fed to ALU 2 via the OR gate 10, 32-bit operation is made with ALU 1, 2, and it is transferred to the bus 8 via the registers 7 and 8.
申请公布号 JPS5471533(A) 申请公布日期 1979.06.08
申请号 JP19770137817 申请日期 1977.11.18
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SHIBAYAMA SHIGEKI;IWATA KAZUHIDE;OKUDA NOBUO
分类号 G06F7/50;G06F7/38 主分类号 G06F7/50
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