| 摘要 |
PURPOSE:To perform a high-certainty PLL (phase synchronizing loop) lock detection. CONSTITUTION:Signal fr' from reference frequency divider 12 is supplied to D-type flip-flop F1, and the Q1 output delayed by this F1 is used as reference signal fr sent to phase comparator 15a and is supplied to another F2 to obtain the Q2 output delayed further. The Q2 output is sent to NAND gate NG2 as fr'' together with the signal obtained by causing signal fr' from frequency divider 12 to pass through inverter I1. Measnwhile, output MG from NG2 is sent to AND gate A1 together with phase error output P-O obtained from NG1 of comparator 15a. That is, the P-O output is masked with MG signals, and the L-DG output is generated from A1 only when the P-O output is over the width of MG signals. Then, switch SW is closed by this output to charge a capactor. |
