| 摘要 |
An electronic circuit arrangement designed to store for an indefinite period a signal voltage of predetermined magnitude briefly applied thereto, comprises a main storage capacitor Cs connected via a first semiconductor switch T1 across a supply of unipolar voltage and via a second semiconductor switch T2 across an ancillary storage capacitor Cx, the latter lying in series with a binary capacitor Ci between two conductors M, PHI 1 across which a clock pulse V PHI 1 is periodically generated. The semiconductor switches are field-effect transistors of the insulated-gate type (IGFETs), the gate of the first IGFET T1 being tied to the junction X between the ancillary storage capacitor Cx and the gate of the binary capacitor Ci; this junction X communicates with the junction S between the two IGFETs and the main storage capacitor Cs in the conductive state of the second IGFET T2 whose gate receives a series of unblocking pulses V PHI 2, lagging behind the clock pulses V PHI 1. The unblocking pulses may be generated at the same cadence as the train of clock pulses, in interleaved relationship therewith; they could also be derived from the junction S between the first IGFET T1 and capacitor Cs by having that junction tied to the gate of the second IGFET T2, the latter thus acting as a diode which conducts after the first IGFET T1 has been turned on to recharge the capacitor Cs. The generator of clock pulses V PHI 1 may serve as the voltage supply for the first IGFET T1 by having one of its conductors, PHI 1, joined to the channel of that IGFET via a third IGFET T3 connected as a diode. |
