发明名称 TEMPORAL MEMORY CIRCUIT
摘要 PURPOSE:To enable to inspect the falure of the write-in operation of the memory circuit immediately after the write-in operation, by feeding the output of two input selection circuit as the address input of the write-in ememory circuit and by inspecting the output. CONSTITUTION:The address register 25 stores the address information given at write-in operation until the next write-in. Further, the tow input selection circuit 26 takes the output of the register 25 as one input and the address information given externally as another input, and the output of the register 25 is selected as the address input for a given time with the clock control. Further, the output of the circuit 26 is taken as the address input the readout and write-in memory circuit 22 and inspect 23 the output of the circuit 22. Thus, the failure in write-in operation of the memory circuit can be inspected immediately after the write-in operation.
申请公布号 JPS5467339(A) 申请公布日期 1979.05.30
申请号 JP19770134503 申请日期 1977.11.08
申请人 NIPPON ELECTRIC CO 发明人 ISHIKAWA AKIHIKO
分类号 G06F12/16;G11C7/00;G11C8/10 主分类号 G06F12/16
代理机构 代理人
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