| 摘要 |
PURPOSE:To increase the noise margin relating to selection and to speed up the circuit operation, by constituting the amplitude of selection signal arbitrarily selectable, in a master-slave FF. CONSTITUTION:When the signal level fed to the sirst selection terminals a, b and second selection terminals c, d are increased than the level more for the terminals a, b than the terminals c, d, the first state is obtained, and if the level for the termianals c, d is higher than that of the terminals a, b, the second state is constitued. The two logic circuits constituted with transistors TrQ35, 36, 37, 38 are provided. Further, TrQ29 to Q34 inputting the selection signal Co to S from external and the voltage VBB and giving the selection signal to the logic circuit through the selection terminals a to d, load resistors Rx1, Ry1, Rx2 and Ry2 are connected in series with the collector, constituting the selection signal generation circuit. Further, by selecting the values of the resistors Rx1, Ry1, Rx2, Ry2 and arbitrarily selecting the amplitude of the signal given to the logic circuit, the potential of the driving points A to D is selected for the master slave type FF. |
