| 摘要 |
PURPOSE:To reduce the current consumption, by setting the output signal level with the first or second CP after setting MOSFET of the gate circuit to a given state with the input signal and by eliminating the switching current. CONSTITUTION:When the input SIN is from H to L, CPphi1 in synchronizing with this is in L for t1, pMOSTQ1,Q2 are sequentially turned on, and the output SOUT is in H. CPphi2 is in L during DELTAt when the Q1 and Q2 are switched and nMOSTQ4 is turned off, and the switching current is very slight. When SIN is from L to H, Q2 is turned off and nMOSTQ3 is turned on. CPphi1 is in L during t1, but SOUT is held at H because Q2 is turned off. After DELTAt, phi2 is in H and Q4 is turned on. At this time, since Q3 is turned on, SOUT is at L. When Q4 is switched, phi1 is already in H and Q1 is turned off, then no switching current is flowed from VDD to ground. Thus, total cosuming current can be reduced. |
