| 摘要 |
A data source is connected through a gating circuit to all stages of an asynchronous shift register. The gating circuit senses the full or empty status of each stage of the shift register and enters an incoming bit of data into that stage of the shift register which is the empty stage nearest the output, and has no stage preceding it which is full. The arrangement decreases the delay time normally encountered by data as it is shifted through the shift register, the decrease in delay time being related to the number of empty stages in the register at the time a bit of data is entered.
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