发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To shorten an access time by simplifying the procedure of partial writing, and to reduce the size of the hardware of a board and work load, by enabling the memory board to function to write partially data to the memory by itself. CONSTITUTION:At the time to writing to the 16-bit memroy partitioned into two 8-bit memroy blocks 11 snd 12, a signal controlling a memory address and memory operation and write data are both transmitted to the memory in sequence via lines 17 and 16, and 14 and 15, and at the time of simultaneous partial writing to the memory, its request signal is sent out to the memory via line 19 and partial write control circuit 13 in the memory board, after receiving signal 19, fetches a bit assignig blocks 11 and 12 from signal 17 and decodes it. On the other hand, since circuit 13 has received one control signal needed for writing fro line 18, either block 11 or 12 is chosen judging from this received control signal and the result of decoding, and data 14 and 15 from the CPU are written to the selected one.
申请公布号 JPS5462734(A) 申请公布日期 1979.05.21
申请号 JP19770129267 申请日期 1977.10.28
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 HIRAOKA TAKASHI
分类号 G06F12/04;G06F12/06;G11C7/22 主分类号 G06F12/04
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