| 摘要 |
PURPOSE:To establish the data fetch circuit enabling the detection of failure, even with the absence of clock. CONSTITUTION:Data are fetched to the register 31 with the clock 1 and data are transmitted to other circuits. After that, the clock 2 sets the register 3, making the output into parity error state. Further, the clock 1 fetches data at next to the register 3, delivering data to other circuits. By repeating this operation, the data are sequentially delivered to other circuits. Moreover, the parity check circuit is masked from the clock 2 to the clock 1. If no clock 1 is present, since the register 3 is in parity error state with the clock 2, the parity check circuit 2 detects parity error. |
