| 摘要 |
PURPOSE:To secure easy investigation for the factors of errors caus by both the software and the hardware by providing the bus check means on the bus line which is common to the input and putput control units. CONSTITUTION:When the interruption signal is delivered to channel 1 from input/ outpout device IOC, COU gives the AKIT order to control line 4 to know which IOC the interruption is given from. Bus check circuit 8 consists of AKIT detecting circuit 10 and device and address detecting circuit 11. Circuit 10 checks whether some interruption signal has arrived from IOC when the AKIT command is given from channel 1. And the soft error signal 9 is emitted to channel 1 in case no interruption signal exists. Circuit 11 memorizes device adress DA of IOC and compares IOC with DA which is given when the data is transferred. And error signal 9 is emitted to channel 1 when no coincidence is obtained. |
