| 摘要 |
PURPOSE:To make error detection for data transfer easy and confirm the operation every bit of interface by providing a matching circuit for inversion collating in an inversion data transmission logic and a simple receiving part. CONSTITUTION:Data ready signals 1R and 2R are transmitted from ready timing circuit 12 of the output interface part to two continuous timing signals 3t and 4t. Meanwhile, in the input interface part, parallel data received by the first timing signal it is stored in receiving data memory 23, and parallel data 2r received by the second timing signal 2t is matched with the output of memory 23 for inversion collation in exclusive logical operation circuit 24. As a result, error detection for data transfer is made easy, and the operation can be confirmed every bit of interface. |
