| 摘要 |
PURPOSE:To constitute a circuit suitable to LSI implementation by using relative b-bit error correcting codes which are able to detect an error of 2 b bits occurring to two blocks. CONSTITUTION:From information 6, check-bit generating circuit 1 generates check bit 7, which is applied to processor 2 together with information 6. Syndrome generating circuit 3 generates a syndrome bit from information 9, and generated bit becomes error-position indication iformation bit 10, which is applied to error correction circuit 5 together with information 8 equivalent to information 6 of output information 9, so that the error will be corrected. |
