| 摘要 |
1329753 Data processor ING C OLIVETTI & C SpA 25 Nov 1970 [25 Nov 1969 25 Sept 1970] 56098/70 Heading G4A Data processor has a store holding a programme, a read only store holding microprogrammes corresponding to a selected set of programme instructions and a logical command unit generating sequentially commands for executing micro instructions and controlling the transfer of data and programme instructions to operational registers and to and from an arithmetic unit. A micro instruction is read from ROM 15 and one of registers 13 which acts as an address is incremented. Execution of micro instructions is controlled by a status register 23 the contents of which are controlled by a field F of 4 fields of the micro-instruction. Read out occurs in a single machine cycle of a timing unit 19 and is identified by a flip-flop of register 23. One or more cycles is required for execution during which the micro instruction remains in register 17, while the contents of register 23 change through four executive states each of which defines the next according to the micro instruction. The logic unit 21 in accordance with the contents, of registers 17, 23 generates control signals. The instructions contain addresses of operands in the core store 11 and register 13 hold data to be operated on, e.g. by arithmetic unit 25 and can act as addressers for the ROM 15 or core store 11 and hold data to be exchanged with the store, a console or a peripheral unit. The addresses may be modified by a register 63. The logic unit controls the flow of data via various AND gates, shown as blocks holding 3 sets of data, which can transfer a given number of bits in various positions, e.g. 0700-0700 transfers 8 bits in parallel and 0300-0704 transfers 4 bits shifted left 4 positions. Fig. 2c shows the input and output gates of the core store and the couplings between the store and the registers 13, 17 allowing supply of addresses and data words and between the store and accumulator registers 39, 41. The control unit 27 controls connections to peripherals via a multiplex channel and supervises the carrying out of microprogrammes of four priority levels in order of priority in the event of a plurality of micro interrupt requests, some of which may be requests for access by a peripheral unit. |
