| 摘要 |
PURPOSE:To decrease the average scale frequency error without increasing the oscillation frequency by realizing a divider circuit featuring the non-integer division number by means of the maximum feedback shift register. CONSTITUTION:In case a division number, for example, 380.5 is obtained, division number detector gate 6 detects state number 253. And duty cycle detector gate 7 detects state number 63, and furhtermore (+1) or (-1 notation) detector gate 8 detects state number 511 which is (-1 notation) respectively. The output of gate 6 sets FF9 and is also applied to shift register 4 via OR12 of gate 6 and EOR13 to make jump the state from 253 to 384. And furthermore the output of FF11 is set to ''1''. Under these conditions, the shift of register 4 is progressed and gate 8 detects state 511, and then AND10 delivers ''1''. Then the shift of register 4 is progressed to shift each state number, thus obtaining the division output featuring average division number of 380.5 as shown in the diagram. |
