| 摘要 |
<p>PURPOSE:To prevent a clock to be supplied to each gate array from generating the difference of delay time by equally distributing a clock wiring in length to respective gate arrays, and concentrating load gates. CONSTITUTION:Since clocks are distributed from 1st clock distributing gates 21 to 24 to flip flops in respective gate arrays 2-1 to 2-4 through short wirings, the delay times of clocks can be reduced and differences among the delay times of respective gate arrays can be reduced. Distances from 2nd clock distributing gate groups 31 to 34 to the 1st clock distributing gates 21 to 24 are respectively equal and distances from the 3rd clock distributing gate groups 41 to 43 to the 2nd gates 31 to 34 are similarly equal. Consequently, distances between load gates in respective groups can be shortened and the difference of delay times is not generated.</p> |
