发明名称 FRAME SYNCHRONIZING SYSTEM
摘要 PURPOSE:To shorten the resynchronizing time by just increasing the register length and through a simple circuit constitution by adding the register to memorize the correlation result along with the means to select the bit at the fixed digit position in each frame and then to secure the correlation between the frames. CONSTITUTION:Input signal S1 is detected for the frame pattern digit at frame pattern detecting part 3, and the correlation is secured with every bit through correlation detector circuit 4 between the frame detection result and the preceding frame detection result. And this result is stored in register 5. In case no correlation is secured, the another correlation is secured with the subsequent frame. While in case the correlation is secured, the number of the frame with which the correlation is secured is counted at control circuit 24. And when the count value exceeds a fixed value and only one bit of the digit securing the correlation is left in register 5, the digit securing the correlation is positioned at the rear end of register 5 with the subsequent frames. Thus, the detection start digit position is always coincided with the digit position where the correlation exists, and then the synchronous lead- in performed.
申请公布号 JPS5456347(A) 申请公布日期 1979.05.07
申请号 JP19770122475 申请日期 1977.10.14
申请人 FUJITSU LTD 发明人 AZAYA TAKAO;YAMAZAWA MASAO;SOEJIMA TETSUO
分类号 H04J3/06;(IPC1-7):04J3/06 主分类号 H04J3/06
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